One type of CMOS P-well memory cell 10 shown in FIG. 1 comprises a first complementary pair of MOS transistors 12 in series with each other between a positive supply V.sub.DD and ground G and a second complementary pair 14 in series with each other between the positive supply and ground. The first pair of transistors 12 comprises an n-channel MOSFET 16 having its source (s) connected to ground and its drain (d) connected to the drain (d) of p-channel MOSFET 18. The source (s) of transistor 18 is connected to supply V.sub.DD. The gates (g) of transistors 16, 18 are connected together. The second pair of transistors 14 comprises an n-channel MOSFET 22 having its source (s) connected to ground and its drain (d) connected to the drain (d) of p-channel MOSFET 26. The source (s) of MOSFET 26 in turn is connected to the supply V.sub.DD. The gates (g) of transistors 22, 26 are connected together. All n-channel transistor substrates are at ground and not shown. All p-channel transistor substrates are at VDD and also not shown.
A first transfer gate MOSFET 32 has its source (s) connected to a positive bit line 36 and its drain (d) connected to the drains (d) of transistors 16, 18, and a second transfer gate MOSFET 34 has its source (s) connected to a negative bit line 38 and its drain (d) connected to the drains (d) of transistors 22, 26.
A first feedback resistor 28 is connected between the gates (g) of transistors 22 , 26 and a n ode (n) interconnecting transistors 16, 18 and similarly, a second feedback resistor 30 is connected between the gates (g) of transistors 16, 18 at another node (n) interconnecting transistors 22, 26.
The first pair of transistors 12 establishes a signal on the positive bit line 36 in response to an address signal applied to the first transfer gate 32. The second pair of transistors 14 establishes a signal on the negative bit line 38 in response to a address signal applied to the second transfer gate 34.
In CMOS memory circuits of the type shown using P-well technology, random ionic interactions tend to cause undesirable coupling of adjacent p-channels or n-channels thereby to result in random memory errors. Dynamic random access memories (DRAMs), which are very sensitive to such ion interactions, lose information due to alpha particles generated from trace contaminants in the package material. Static random access memories (SRAMs) are less sensitive to low mass ions but undergo random hit losses when hit by heavier particles present in cosmic rays. Such particles may be encountered especially in outer space applications such as in satellites or spacecrafts orbiting the earth.
Semiconductor memories are susceptible to random errors caused by the interaction of energetic ions with the semiconductor material. When an ion penetrates the semiconductor, a localized charge packet is generated, which due to junction built-in electric fields and externally applied voltages, may appear as transient currents within the individual cells of the memories.
The feedback resistors 28, 30 are somewhat effective to reduce the transient currents and thereby reduce random errors occurring as a result of loss of information with cosmic ray interactions and other random hit losses. Indeed, CMOS P-well type SRAM memory cells of the type shown in FIG. 1 are commonly used in 16K memory chips; however, two problems are encountered in making 64K memory chips using this technology. First, the absolute value of the feedback resistors 28, 30 in memory units larger than 16K will increase the writing time for the units. This will have a deleterious effect on performance.
Second, the feedback resistors 28, 30 must be large. Since polysilicon resistors have large temperature coefficients, large changes in resistance occur with temperature change. Since the resistance value of each feedback 28, 30 resistor drops dramatically with increasing temperature, the low temperature value is much larger than that required to protect the cell, further increasing the writing time. It accordingly is desirable to improve upon presently known memory cells so as to cause them to be substantially immune to random errors due to energetic ionic interactions while maintaining good performance characteristics.